1. Field of the Invention
The present invention relates to a circuit arrangement using compensation capacitors designed to secure a minute signal from a bit line which is input to a sense amplifier in a dynamic semiconductor memory device.
2. Description of the Prior Art
The progress in shrinkage technique in recent years has introduced a tendency towards highly-integrated semiconductor memory devices with large capacity. Particularly, a dynamic random access memory device (referred to as a DRAM hereinafter) leads the trend.
In the DRAM, one-bit data is stored as electric charge in a memory cell comprised of one transistor and one capacitor. When a high signal is input from a word line corresponding to an input row address to a gate of the transistor, the capacitor where the data is stored is connected with a precharged bit line. The potential change of the bit line at this time is amplified by a sense amplifier between the bit line and a reference line in pairs, and transmitted to an output circuit.
The data is read out from the conventional DRAM described above in a manner as follows.
FIG. 4 is a circuit diagram showing the structure of a memory cell array part and the sense amplifiers SA.sub.1, SA.sub.2, . . . , SA.sub.m of the conventional DRAM. Each sense amplifier is comprised of a differential amplifier consisting of a pair of N-type transistors, for example, QN1, QN1', and a pair of P-type transistors, for example, QP1, QP1'. Two bit lines BL1, BL1 are connected to the sense amplifier SA1 as one pair of inputs. Each bit line BLi (i=1 to m) or BLi is connected to each data memory capacitor mCi.1 or mCi.2, which is connected between a MOS transistor Qi.1 or Qi.2 as a transfer gate and a fixed voltage electrode Vcp. The MOS transistor acting as a transfer gate is controlled in response to the selection of a word line among word lines WL1 WL2, . . . , WLn. A common node SAP of the P-type transistors and a common node SAN of the N-type transistors of the sense amplifier are connected to precharging transistors Qp, QN and an equalizer transistor QEQ, respectively.
The operation of the conventional DRAM having the circuit structure shown in FIG. 4 will be described with reference to FIG. 5, which is a schematic timing chart of the operation and waveforms of the conventional DRAM.
First of all, the reading operation will be explained by way of example. In the stand-by period before reading, as indicated in the timing chart, a clock .PHI..sub.1 is set at Vcc and the equalizer transistor QEQ is turned on thereby, with a clock .PHI..sub.2 being set at 0 and a clock .PHI..sub.3 being set at Vcc, thereby turning off the precharging transistors QN and QP. Accordingly, the common node SAP (referred to as SAP hereinafter) and the common node SAN (referred to as SAN hereinafter) are set at 1/2 Vcc, and the transistors QN1, QN1', . . . , QNm and QNm' for driving the sense amplifier are kept in the off state. Moreover, bit lines are set at 1/2 Vcc by means of equalizer transistors and precharging transistors (not shown in FIG. 4). When the DRAM is driven for access, the clock .PHI..sub.1 is turned to 0 thereby turning off the equalizer transistor QEQ, releasing the connection between SAP and SAN. The level of a word line corresponding to the input address is raised at a next timing. As a result, capacitors connected to the word line are connected to the respective bit lines and the level of each bit line is changed in response to each charging state corresponding to the data memorized in each capacitor. At a succeeding timing, SAN is set at 0 by turning the clock .PHI..sub.2 to Vcc, and SAP is set at Vcc by turning the clock .PHI..sub.3 to 0. When SAP is set at Vcc, each sense amplifier detects the above level change, and amplifies the level of the corresponding bit line to Vcc or 0. For example, when the potential of word line WL1 is raised, as indicated in (b) of FIG. 5, the transistor Q1.1 is turned on thereby and, accordingly, the capacitor mc1.1 is connected to the bit line BL1. If it is in the not charge state, a negative level change .DELTA.V is given to the bit line BL1 as shown in (g) of FIG. 5. Therefore, the bit line BL1 is moved to 0 due to a differential amplification between .DELTA.V and 1/2 Vcc of the corresponding bit line BL1, which is not changed by the word line WL2, so that the bit line BL1 is moved to Vcc. The same change is brought about in the other capacitors mc2.1, . . . , mcm.1, connected to the word line WL1. In the manner as above, the charging state of each capacitor corresponding to the word line is read out as the level change of each bit line. When the reading operation is completed, the potential of the word line is finally turned off after a predetermined reset period. The level of each bit line is thus held in the respective capacitor.
In the conventional DRAM mentioned above, all the currents read out from respective capacitors corresponding to the word line flow into a Vss line. At this time, the falling state of the aforementioned SAN is affected by the impedance of Vss, which is reflected to the operation of the differential amplifier, thereby causing a delay in the level shift of the bit line.
This will be explained in more detail with respect to the case where the capacitor mc2.1 is in a charged state. Assume that SAN and SAP are driven by raising the potential of clock .PHI..sub.2 to Vcc and then dropping the potential of clock .PHI..sub.3 to 0 after the word line WL1 is raised, as indicated in (c) and (d) of FIG. 5. When WL1 is raised up, the level of BL1 is reduced by .DELTA.V, while that of BL2 is increased by .DELTA.V, as shown in (g) and (h) of FIG. 5. Thereafter, SAN starts to fall to 0. At this time, SAP, BL1 and BL2 remain at 1/2 Vcc, and the P-type transistors of each differential amplifier are kept in the off state, whereas only the N-type transistors are driven due to the potential difference between the gate and SAN. It is so designed that the potential difference to turn on the N-type transistors at this time should exceed the aforenoted .DELTA.V. Therefore, as indicated in the timing chart of FIG. 5, no level change is produced by the .DELTA.V change of the bit line caused by the word line. Subsequently, almost at the same time when SAN starts to fall by the rise of the clock .PHI..sub.2, QN2' allows a current to flow since it starts with the potential difference .DELTA.V from the beginning, and BL2 alike starts to fall. Meanwhile, although QN2 starts from the potential difference 0, it is turned off due to the level fall of the gate by BL2, and BL2 is maintained at 1/2 Vcc+.DELTA.V. On the other hand, since QN1' starts from a disadvantageous potential difference, i.e., the gate is .DELTA.V lower than the source, the change of the QN' level is behind the fall of the SAN level, and BL1 remains at 1/2 Vcc until then. QN1 is, starting from the potential difference 0, slower to fall than SAN. The BL1 level is maintained at 1/2 Vcc-.DELTA.V until then. As the above-described operation is carried out for many capacitors, a current equivalent to the reading current of QN2' is produced at many capacitors. Therefore, when the impedance of Vss line is high, as shown in (f) of FIG. 5, .DELTA.Vss voltage is generated in Vss line and the SAN level is raised as indicated in (e) of FIG. 5. As a result, QN1 and QN1' are hindered from being changed in level, delayed until SAN recovers to Vss after the capacitors are completely discharged. Thereafter, when the clock .PHI..sub.3 is dropped to 0 in order to raise SAP to Vcc, BL1 and BL2 are raised to Vcc in correspondence to the level fall of BL1 and BL2, respectively. Waveforms in FIG. 5 represent the result of the delay in total. The delay in the level change of the bit lines as noted hereinabove necessitates a waiting time for the sense amplifier to obtain the driving margin, making it hard to achieve high-speed access.